Decoupling capacitors are usually placed on integrated circuit (IC) packages between external power sources and the delicate circuitry contained in the package. Commonly, such decoupling capacitors are used to buffer the circuitry of the package from power fluctuations common in the external sources. Such fluctuations can be fatal to delicate or less robustly designed circuitry of the package. Decoupling capacitors are useful for ameliorating such effects. Also, decoupling capacitors can provide on package power sources that provide excellent steady state sources of direct current to the circuit elements of the package. Such decoupling capacitors find many other uses that are readily apparent to those of ordinary skill in the art.
However, as appreciated by those having ordinary skill in the art, due to the relatively large size of such decoupling capacitors and the need to make electrical connections to power or ground lines deep within the package, significant alterations must be made in the layout of the signal layers to accommodate the capacitors. Accordingly, the signal trace patterns of the signal layer must be designed with the decoupling capacitors in mind. In current designs, the addition of decoupling capacitors necessitates the crowding of the traces of the signal layers in order to facilitate electrical connections that must pass through the signal layers to connect with underlying layers. Thus, commonly the signal layer layout for a design incorporating decoupling capacitors bears no resemblance to a signal layout designed for use without decoupling capacitors even though both layouts are intended to accomplish exactly the same function. As can readily be appreciated, having two designs required for the same purpose is inefficient and expensive. Moreover, a design initially conceptualized for use without decoupling capacitors cannot be readily or easily converted to add decoupling capacitors at some later time without considerable expense.
The following paragraphs illustrate some further aspects of the problems existing in the current state of the art. Due to the reasons explained above, as well as reasons to be articulated below, the decision as to whether to add decoupling capacitors must be made early in the design process. This can pose a major problem. For example, if a designer or customer desires to make use of a previously tooled or generic package they do not have the option of using decoupling capacitors unless the previously designed package includes decoupling capacitors. The addition of such capacitors is expensive, accordingly such capacitors are only added if absolutely necessary. Additionally, if a package designed for use without decoupling capacitors is used, the cost will be less, but detrimental effects on package performance will be introduced.
FIG. 1 depicts a schematic side sectional view of a six-layer package structure. The depicted package 100 includes six layers 101, 102, 103, 104, 105, 106 arranged in a stripline configuration. Generally speaking, a stripline is package configuration includes a pair of reference planes having at least one signal plane sandwiched therebetween. The reference planes can, for example, be a pair of ground planes or a pair of power planes and can also be a ground plane and a power plane. One such example is depicted by FIG. 1 which depicts stripline 121. The stripline 121 includes a first layer 101 with a ground plane (Vss) 116 and a second layer 102 with a signal plane 114 and a third layer 103 with a power plane (Vdd) 112. The planes are interconnected using a plurality of conductive vias 111. In the depicted embodiment the ground plane 116 includes a plurality of bond pads 119 configured for attachment to other circuit elements of the package. Also, typically the first layer includes a patterned solder mask 118. In the depicted six-layer package, another bottom stripline 122 is depicted.
In existing designs, when a decoupling capacitor is used the capacitor is electrically connected with the top ground plane 116 and also to an underlying power plane 117 (or alternatively 112). This requires that a via be formed that passes through the signal planes 113, 114 to enable such connection. FIGS. 2(a) and 2(b) illustrate, in simplified depiction, the effects of the via on the pattern of signal traces. FIG. 2(a) depicts an example signal trace pattern formed on a signal plane. The dashed line 201 depicts the position of a via for connecting the decoupling capacitor. As can be seen in FIG. 2(b), considerable rearrangement of the traces are required to accommodate the via 202. This causes considerable trace crowding and can lead to cross talk between the traces. Also, the close proximity of the traces to the via itself can induce many undesirable effects.
Current solutions to the problem can include complete redesign of the package to add decoupling capacitors. This is particularly time consuming, especially with respect to the redesign of the signal planes which involve a great deal of expensive engineering time in order to achieve. This type of redesign results in greater cross talk between adjacent signal traces and requires redesign of all layers of the package design.
Presently there are no satisfactory processes for converting packages designed for use without decoupling capacitors into packages for use with decoupling capacitors. As stated above, there is a need for process methods for achieving such conversion and also for packages capable of operating with decoupling capacitors and without decoupling capacitors.